Integrated circuits are formed on a semiconductor die and packaged for incorporation into a variety of end products. Examples of semiconductor chip packages include general purpose processors, graphics processing units, memory chips and a variety of specialized application specific integrated circuits (ASIC).
Packaging integrated circuits typically entails placing a die on a carrier such as substrate, a lead-frame or a circuit board and forming electrical connections between interface pads on the die and conductive traces on the carrier. The carrier includes solder balls or pins which are suitable for mounting the package on external devices such as motherboards, expansion cards, and the like. The conductive traces provide electrical interconnection to solder balls or pins on the carrier.
A variety of packaging techniques are commonly used. These include flip chip packaging and wire bonding. In wire bonding, the inactive surface of the die, away from the circuitry, is attached to a carrier, and wires are bonded to die pads on the die on one end, and to conductive traces on the carrier substrate at the other end of the wire.
In flip chip packaging however, the active surface of the die faces the carrier substrate when the die is attached. Small amounts of solder called solder bumps are formed on each die pad of the die and used to connect each die pad on the die to a corresponding conductive trace on the carrier. Under bump metallization (UBM) is typically formed over each pad, to provide a low resistance electrical connection to solder bumps. Each conductive trace connects to a corresponding solder ball to provide external I/O connection points. The solder balls are used to attach the semiconductor package to an external printed circuit board (PCB).
Flip-chip packaging is generally regarded as providing smaller package sizes, higher performance, greater input/output (I/O) density and lower cost as compared to wire-bonding.
Semiconductor packaging may be performed per each die, or at the wafer level. In wafer level packaging, instead of applying packaging techniques to individual dies, packaging techniques are applied to all the dies on a fabricated wafer at once. As a last step, the wafer is separated or cut into individual packaged dies ready for assembly onto an external board. Flip chip packaging techniques can be applied at the wafer level to form individual semiconductor packages.
Solder bumps may be subjected to thermo-mechanical stress. A common source of thermo-mechanical stress is a mismatch in the coefficient of thermal expansion (CTE) between the die and the carrier. During operation, heat is invariably generated by integrated circuits, which causes both the die and the carrier to expand. As the CTE for the die may be substantially different from the CTE of the carrier, this dissimilar rate of expansion causes thermo-mechanical stress on the solder bumps. If the stress is sufficiently large, it may damage the physical connection provided by solder bumps and as a result electrical connectivity may be lost.
One well known technique to reduce thermo-mechanical stress in flip-chip attachments is underfilling, which entails introducing additional material (called underfill) such as epoxy resin between the die and the carrier after the die is attached onto the carrier board. This reduces the stress on the solder bumps, thereby improving the package's reliability.
However, underfilling is disadvantageous as it entails an additional manufacturing step and makes disassembly of semiconductor packages difficult.
Accordingly, there is a need for new chip packaging techniques.